1. Technical Field
This invention relates to a digital phase locked loop apparatus including a phase locked loop circuit, which generates a reproduction clock in synchronism with reproduction data of an optical disc apparatus or a magnetic disc apparatus, as well as a recordation clock in synchronism with a wobble signal of the optical disc apparatus.
2. Discussion of the Background Art
A phase synchronization loop circuit (a phase locked loop circuit) is utilized in a data reproducing apparatus that reproduces data from a rotational storage medium, such as an optical disc, a magnetic disc, etc., to obtain a clock that synchronizes with reproduction data. The phase locked loop circuit is almost realized by an analog circuit that employs a voltage-controlled oscillator. However, a self-running frequency of such an analog voltage controlled oscillator tends to vary in accordance with a change in environment temperature or power supply voltage, thereby resulting in a long pull-in time of the phase locked loop circuit. Then, a digital phase locked loop circuit has been proposed as discussed in Japanese Patent Application Laid Open No. 60.245312.
Since the digital phase locked loop circuit does not employ an analog voltage controlled oscillator, the above-mentioned variation does not occur, and a self-running frequency is stable with a frequency clock precision (i.e., crystal precision) provided as a reference. Further, since being entirely configured by a digital circuit, the digital phase locked loop circuit can be easily mounted on an integrated circuit, thereby an apparatus can be downsized and is low cost.
FIG. 25 is a block diagram illustrating an exemplary configuration of a conventional digital phase locked loop circuit. FIG. 26 illustrates an operational wave appearing in the digital phase locked loop circuit of FIG. 25. The digital phase locked loop circuit includes a phase comparator 700, a counter 701, an incrementer-decrementer 702, and a divider 703.
The digital phase locked loop circuit needs a high frequency clock as an operational clock PC2 used in the phase locked loop when time resolution of a phase of an output clock FS thereof is to be enhanced. For example, a frequency of thirty-two times of a reproduction data rate is required as an operational clock in the digital phase locked loop circuit when time resolution of an output clock phase of the digital phase locked loop is to be thirty-two times of the reproduction data rate.
However, recordation and reproduction speeds for a CD and a DVD have significantly increased, and recently, the internal operational clock frequency has become extraordinarily high in the above-mentioned conventional digital phase locked loop circuit.
As a result, it exceeds an operation frequency limit for the circuit, thereby the digital phase locked loop circuit becomes inoperative when the reproduction data rate is large. This invention is made in view of the above-mentioned aspects, and it is an object of the invention to achieve a fine time resolution of an output clock phase while using a relatively low frequency of an operational clock.